A. Field of the Invention
This invention relates to a semiconductor device.
B. Description of the Related Art
Generally, semiconductor devices are classified into horizontal semiconductor devices having electrodes on one side and vertical semiconductor devices having electrodes on opposite sides. In a vertical semiconductor device, a direction in which a drift current flows in the ON state coincides with a direction in which a depletion layer spreads due to a reverse bias voltage in the OFF state. For example, in an n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with an ordinary planar gate structure, a high resistivity n− drift layer portion operates as a region where a drift current flows vertically in the ON state. Accordingly, drift resistance is reduced when the current path of the n− drift layer is shortened. It is therefore possible to obtain an effect that substantial on-resistance of the MOSFET can be reduced.
On the other hand, the high resistivity n− drift layer portion is depleted in the OFF state to thereby increase breakdown voltage. Accordingly, as the n− drift layer is thinner, the width with which a drain-to-base depletion layer spreads starting at a pn junction between a p-base region and the n− drift layer is narrowed so that the breakdown voltage reaches the critical field strength of silicon more quickly. Thus, the breakdown voltage is lowered. On the contrary, in the semiconductor device with high breakdown voltage, the n− drift layer is so thick that on-resistance becomes high enough increase the loss. In this manner, there is a tradeoff relationship between the on-resistance and the breakdown voltage.
It has been known that this tradeoff relationship is also established in semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor and a diode. In addition, this tradeoff relationship is also common to horizontal semiconductor devices in each of which a direction where a drift current flows in the ON state is different from a direction where a depletion layer spreads due to a reverse bias voltage in the OFF state.
As a solution to the problem caused by the tradeoff relationship described above, there has been known a superjunction semiconductor device having a drift layer arranged into a parallel pn structure in which an n-type drift region and a p-type partition region are joined to each other alternately and repeatedly with an enhanced impurity concentration (for example, see U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215 and JP-A-9-266311). In the semiconductor device having such a structure, a depletion layer spreads horizontally from each pn junction extending in the vertical direction of the parallel pn structure to thereby deplete the whole of the drift layer in the OFF state in spite of the high impurity concentration of the parallel pn structure, so that the breakdown voltage can be increased.
On the other hand, in a semiconductor device provided with a diode or in a circuit using a parasitic body diode of a MOSFET etc. such as a bridge circuit, it is necessary to prevent the device from being broken down even when high di/dt occurs during reverse recovery of the diode. As a solution to such a problem, there has been proposed that the carrier lifetime of a parallel pn structure in an edge termination region is made shorter than the carrier lifetime of a parallel pn structure in an active region so that a current flowing into the active region from the edge termination region can be reduced to improve the reverse recovery capability (for example, JP-A-2003-224273, JP-A-2004-22716 and Japanese Patent No. 4743447). Japanese Patent No. 4743447 describes integration of a diode with a MOSFET, but has no suggestion about formation of a p-type region in a drain region opposite to an edge termination region of a MOSFET.
The configuration of a prior art superjunction MOSFET to which such a local lifetime technique is applied will be described. FIG. 18 is a cross sectional view showing the structure of a vertical MOSFET according to the prior art. FIG. 18 corresponds to FIG. 12 in JP-A-2004-22716. As shown in FIG. 18, drain drift portion 102 with a first parallel pn structure is provided on low resistivity n+ drain layer 101 with which drain electrode 113 on the back side makes ohmic contact. Each p-base region 103 having a high impurity concentration and serving as an active region 121 is provided selectively in the surface layer of drain drift portion 102.
Drain drift portion 102 substantially corresponds to a portion just under p-base regions 103 including a plurality of wells and serving as active region 121. Drain drift portion 102 has a first parallel pn structure in which a vertically layer-shape first n-type region 102a oriented in a thickness direction of a substrate and a vertically layer-shape first p-type region 102b oriented in the thickness direction of the substrate are joined to each other alternately and repeatedly along a surface of the substrate at a repeated pitch P101. An MOS gate structure (metal-oxide film-semiconductor insulating gate) including p-base regions 103, p+ contact regions 105, n+ source regions 106, gate insulating film 107 and gate electrode layer 108 and source electrode 110 are provided on the front side of the first parallel pn structure. Reference numeral 109 indicates an interlayer insulating film.
Drain drift portion 102 is surrounded by edge termination region 122 including a second parallel pn structure. Edge termination region 122 is provided consecutively to the first parallel pn structure of drain drift portion 102. In edge termination region 122, a vertically layer-shape second n-type region 112a oriented in the thickness direction of the substrate and a vertically layer-shape second p-type region 112b oriented in the thickness direction of the substrate are joined to each other alternately and repeatedly along the surface of the substrate at a repeated pitch P101. The repeated pitch P101 of the first parallel pn structure is substantially equal to that of the second parallel pn structure and the impurity concentration of the first parallel pn structure is substantially equal to that of the second parallel pn structure.
Oxide film 115 is provided on the surface of the second parallel pn structure. A field plate electrode FP extended from source electrode 110 is formed on oxide film 115 to thereby cover the part of the second parallel pn structure. N-type channel stopper region 114 connected to n+ drain layer 101 is formed on the outer side of edge termination region 122 and stopper electrode 116 makes ohmic contact with n-type channel stopper region 114. The second parallel pn structure and n-type channel stopper region 114 serve as a region (indicated as a hatched portion) shorter in carrier lifetime than the first parallel pn structure.
However, in JP-A-2003-224273, JP-A-2004-22716 and Japanese Patent No. 4743447, the carrier lifetime of the second parallel pn structure in edge termination region 122 is made shorter than that of the first parallel pn structure in active region 121 so that the quantity of stored carriers in edge termination region 122 can be reduced to suppress destruction by local crowding of a reverse recovery current during reverse recovery of a body diode including first p-type regions 102b and first n-type regions 102a. However, the leakage current in the OFF state increases due to the shortened carrier lifetime of the second parallel pn structure in edge termination region 122. As a result, there is a problem that the loss increases. In addition, when the leakage current increases excessively in the off state, there is a problem that the device breaks down due to thermal runaway.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.